MELVILLE, N.Y., April 8, 2021 /PRNewswire/ — Canon U.S.A., Inc., a leader in digital imaging solutions, today announced that its parent company, Canon Inc., has launched the FPA-5520iV LF Option for back-end process semiconductor lithography systems. This device features an i-line stepper1 with a 1.5 micrometer2 resolution and a wide exposure field of 52 mm x 68 mm for advanced packaging3.
In the field of semiconductor chip performance enhancement, alongside the miniaturization of circuits in front-end process of semiconductor manufacturing, higher-density packaging in back-end processes has become a valuable resource within this market. Advanced packaging with high performance requires fine redistribution layer patterns4, and in recent years, semiconductor lithography systems have been used for this purpose. Inheriting the same basic functionality of its predecessor model, the FPA-5520iV, released in July 2016, the new FPA-5520iV LF Option for advanced packaging achieves a wide exposure field of circuit patterns to meet a variety of advanced packaging needs including heterogeneous integration5.
As a result of its projection optical system, the Option recognizes single exposure with a large field of 52 mm × 68 mm — more than four times the standard exposure field (26 mm x 33 mm) of front-end process lithography systems, making support for integrations possible, in which multiple large semiconductor chips are bonded. In addition, with a high resolution of 1.5 micrometers, it is possible to expose fine redistribution layer patterns, thus supporting a variety of advanced packaging types. What’s more, by introducing this high resolution option, redistribution layer patterns can be exposed with a high resolution of 1.0 micrometers.
The FPA-5520iV LF Option inherits the basic performance of the FPA-5520iV, which has received praise for its ability to handle warped reconstituted substrates6, an issue which can occur in packaging layers during the mass-production process. This system also offers enhanced availability by detecting alignment marks on the reconstituted substrates with large chip array variations.
The back-end process of semiconductor manufacturing
In the semiconductor chip manufacturing process, the semiconductor lithography system plays the role of «exposing» the circuit patterns. In the series of lithography processes, the process of forming a semiconductor chip on a silicon wafer is called the «front-end process.» Meanwhile, the «back-end process» entails sealing a delicate semiconductor chip in a package, known as the «packaging process,» to protect it from the external environment and to enable electrical connection with the external portion.
The Canon Lithography System website
The «Canon Lithography System Website» features easy-to-understand explanations, including illustrations and videos, of the technologies behind semiconductor lithography, as well as a dedicated page for kids.
About Canon U.S.A., Inc.
Canon U.S.A., Inc., is a leading provider of consumer, business-to-business, and industrial digital imaging solutions to the United States and to Latin America and the Caribbean markets. With approximately $30.4 billion in global revenue, its parent company, Canon Inc. (NYSE:CAJ), ranks third overall in U.S. patents granted in 2020† and is one of Fortune Magazine’s World’s Most Admired Companies in 2020. Canon U.S.A. is dedicated to its Kyosei philosophy of social and environmental responsibility. To keep apprised of the latest news from Canon U.S.A., sign up for the Company’s RSS news feed by visiting www.usa.canon.com/rss and follow us on Twitter @CanonUSA.
† Based on weekly patent counts issued by United States Patent and Trademark Office.
Availability and other specifications are subject to change without notice.
1 A semiconductor lithography system that utilizes a 365 nm wavelength mercury lamp as the light source. 1 nm (1 nanometer) = 1 billionth of a meter.
2 1 micrometer = one millionth of a meter = one thousandth of a millimeter.
3 Protects delicate semiconductor chips from the external environment and allows them to be electrically connected to the outside at the implementation.
4 Fine wiring for connecting between semiconductor chips or between semiconductor chips and bumps (protruding connecting electrodes).
5 Packaging to combine different chips such as CPU and DRAM, or CPU and GPU. The chips can be placed close together and connected by a number of circuits to increase processing capability.
6 Wafers created by attaching and encasing in resin multiple individual semiconductor chips that are produced during the front-end processes of semiconductor manufacturing.
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SOURCE Canon U.S.A. Inc.